1. Field of the Invention
The present invention relates to a semiconductor memory device, for example, a semiconductor memory device such as an SRAM, of which word line is split to support byte write and so forth.
2. Description of the Related Art
An achievement of low power consumption in an LSI requires a low supply voltage, of which lower limit is though determined by an SRAM in the LSI in many cases. On the other hand, in a memory cell of the 6-transistor type used in the conventional SRAM, data becomes unstable when a word line is selected because a node contained in a flip-flop is slightly pulled up. Therefore, operation with a low supply voltage may destruct data and cause a disturbance phenomenon possibly.
As a measure against such the disturbance problem, an SRAM using memory cells of the 8-transistor type having a read port separated is proposed (Document 1: L. Chang, et al., Symposium on VLSI Technology 2005, p 128). In the memory cell of the 8-transistor type, a node in a flip-flop is not pulled up even when a word line is selected at the time of read. Therefore, the stability of data in the flip-flop increases and the data destruction can not be caused easily. Even in this case, however, at the time of write, it operates in a similar manner as the conventional memory cell of the 6-transistor type. Accordingly, avoidance of the disturbance problem at the time of write requires writing to all memory cells of which write word line is selected.
In general, an SRAM requires a byte write function of controlling data write at a unit of one byte. With this regard, the use of the memory cells of the 8-transistor type to avoid the disturbance problem and realize the byte write function causes a requirement of splitting and controlling a word line at a minimum write unit, that is, on a byte basis. Therefore, it is required to provide word line drivers by the number of split, which increases the chip area.
A cell array in the SRAM has a layout that utilizes the periodicity of the layout pattern, which is higher in dense than general logic circuits. Therefore, dummy cells are required at the outer circumferential ends of the cell array to ensure the periodicity. In particular, when the word line drivers are provided on a byte basis as described above, dummy cells are required on a byte basis and cause a further increase in chip area as a problem.